High-speed digital communication channels or links often employ implicit synchronization with the source clock embedded in the transferred data. To interpret the input data correctly in another synchronous system or clock domain the source clock must first be recovered from the often sparse data transitions occurring in an irregular pattern. A fundamental object for any clock recovery mechanism is to extract timing information from an incoming data stream without the explicit knowledge of the source clock, hence the label embedded clock is often used to state that no explicit clock accompanies the input data.
A clock signal is merely a regular data pattern alternating between marks and zeros (0101 . . . ). In general, a non-coded data stream contains significantly less synchronization information or transitions than a regular clock signal since the logic state may remain unaltered for more than one clock cycle.
Synchronous digital systems involve sequential storage elements, often implemented using asynchronous combinatorial feedback networks, that are updated synchronous to the logic state transition of a system clock signal, i.e. low to high or reverse for a negative edge triggered system. Hence a retiming circuit is required to continuously align an asynchronous sample or system clock to the incoming data. In such a system, an independent local clock source located at the receiver side will be synchronized to the incoming source clock rate.
Receiving the input data correctly hence necessitate a clock recovery mechanism that ensures sampling of the input data ideally in the middle of the data bit. Unfortunately Non Return to Zero (NRZ) encoding is widely used, which in turn does not prevent long sequences of marks (logical high state or one) or zeros (logical low state or zero) in a row. Aligning a sample clock to the incoming data is thus a difficult task when there is little synchronization information (edge transitions) available due to NRZ type of coding schemes.
Conventional accurate data receivers designed to operate without malfunction over a wide range of conditions are often sensitive to excessive input data cycle-to-cycle variations. Severe limitations in the clock recovery mechanism tend to impose unnecessary restrictions on the input data variation.
Common practice of clock recovery is to employ a resonant circuit, often denoted a Q-tank, which has good filtering characteristics but also give rise to a large amount of jitter when the resonant circuit is left unaided between the data transitions (drift towards the natural resonant frequency). Naturally a more precisely tuned Q-tank has a resonant frequency, which is at least closer to the ideal source clock frequency, but there is always a residual frequency drift (due to source tolerances) especially with NRZ coded data that is not rich in the transitions necessary to guide the resonant circuit properly. Note also that a low loss (high Q) resonator has a very narrow band of acceptable input frequencies and thus may reject an offseted source totally with a significantly reduced flexibility at hand.
Various all-digital solutions have emerged to address this and other shortcomings of the analog approaches. Phase locked loops (PLL) together with transition detectors converting the input data to a format, which is richer in transitions and hence allow conventional phase lock techniques to be applied. On the down side is the inherent low pass filtering characteristic of such a phase locked loop. High frequency jitter on the input data signal cannot be tracked (followed) which pose a limit on the final or limit jitter tolerance of the digital clock recovery circuit. A class of particularly interesting and useful clock recovery circuits is based upon the usage of multiphase sample clocks that are asynchronous to the input data, as described for example in U.S. Pat. No. 4,189,622, U.S. Pat. No. 4,415,984, U.S. Pat. No. 4,821,297, U.S. Pat. No. 4,977,582, U.S. Pat. No. 5,488,641, U.S. Pat. No. 5,822,386, U.S. Pat. No. 6,044,122, U.S. Pat. No. 6,130,584, European Patent Application 0 390 958, and European Patent Application 0 480 165. Typically, a number N of equally spaced sample clocks with a period close to the largest input data bit rate is supplied by a delay locked loop or similar means and used for parallel transition edge detection. However, the predominant trend for conventional multiphase clock recovery systems is to employ a centralized clock mux control mechanism of high complexity for updating the phase of recovered clock to more or less accurately fit the desired predetermined relation to the detected input data transitions. In that process, the recovered clock and the input data transitions are compared, but the instantaneous parallel transition indication information is terminated by the centralized control mechanism in the usual increment/decrement manner associated with feedback-based clock synthesis. Unfortunately, step-wise feedback regulation generally results in poor acquisition performance, as well as relatively slow phase tracking response once acquisition has been completed.